1. Technical Field
The present invention relates generally to microprocessor power consumption, and more particularly, to power consumption reduction for a microprocessor derived from a machine code builder.
2. Related Art
Power management in computer systems has become increasingly important as the trend towards more portable computers continues. In particular, the computer industry is using more powerful microprocessors having more internal circuitry and running at faster speeds. However, battery technology has not advanced sufficiently to keep up with the increasing power consumption of current portable computers. To address this problem, various power management techniques have been implemented that aim to reduce power consumption.
A conventional microprocessor may include a variety of special function units or resources that are used to execute instructions more efficiently, saving power and increasing performance over software. A non-exhaustive list of such units may include a floating point unit, a coprocessor, a branch prediction unit, etc. Many power management techniques focus on reducing the power consumption of these units. In particular, as leakage standby power becomes a more dominant portion of total processor power, it is desirable to turn off units when possible.
Two general schema exist for enabling power management techniques. The first includes dynamically controlling the power provided to microprocessor units using hardware logic. The second includes placing power management processing burdens on software rather than microprocessor hardware.
With regard to dynamic control techniques, PowerPC microprocessors, available from IBM among others, are one example where power consumption is dynamically controlled by monitoring an instruction stream and de-activating units not required to execute the instructions. A problem with dynamic control is that it requires power consuming hardware to continuously monitor and decipher the instruction stream.
U.S. Pat. No. 5,996,083 to Gupta et al. is an example of the evolving technique of placing power management processing burdens on the software rather than the microprocessor hardware. In Gupta et al., a microprocessor with a power control register for each functional unit is described. Gupta et al. state that software adjust settings of the power register for a respective functional unit. The power register controls the power consumption of the respective functional unit by controlling, for example, the clock frequency or voltage supply. Gupta et al., however, assume that the software knows what values should be written to the power control register, and provides no instruction on how the software determines which functional units will be managed.6] Another example of software controlled power management is the Crusoe processor from Transmeta, which is an x86-based CPU chip. The Crusoe processor employs a methodology in which a software translation layer turns x86 instructions into Crusoe instructions. In addition, the processor interprets instructions and recognizes repeat instruction sets. To minimize power consumed in translation, the information is stored in a translation cache and the stored block may be reused for a repeat instruction.
Another issue with software controlled power management is that software is conventionally organized for performance in terms of speed-efficiency, and not efficient power consumption. For example, software may be arranged for speed in such a way that a particular functional unit is called at many different points during execution. When this software is implemented, it may result in the functional unit having its power consumption adjusted many times during execution. In many cases, this continual fluctuation of power consumption reduces power savings, which may also diminish performance. One particular software optimization technique includes profile-directed compilation to improve performance. Feedback recompilation uses the profile data generated during the previous run to perform run-time optimizations such as basic block reordering to reduce the number of mis-predicted branches and instruction cache misses. Unfortunately, none of the above-described optimization techniques have been applied with a focus on power consumption and performance.
Another challenge of conventional power management techniques is maintaining performance. For instance, a functional unit may be turned on and off frequently in a software controlled power management scheme. While this saves some power, it drastically impairs performance because it may take many cycles (e.g., >1000) on a multi-GHz processor for a resource to be re-energized. Gupta et al. attempt to address this situation by temporarily stalling operation of the microprocessor until the selected functional unit is at full power. This solution, however, does not address the loss of performance existing during the re-energization of the resource.
In view of the foregoing, a need remains for power management techniques and architecture that do not suffer from the problems of the related art.